Intel's 1986 ICCD paper Performance Optimizations of the 80386 reveals how tightly this was optimized. The entire address translation pipeline -- effective address calculation, segment relocation, and TLB lookup -- completes in 1.5 clock cycles:
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{ 24, 10, 12, 26, 35, 47, 49, 37 },
晚上6点10分，电话铃声再次响起来，阿爸又站起来接电话，对方催促阿爸快点过去，要开饭了。